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Siemens Digital Industries Software Senior Product Engineering Manager in Fremont, California

Job Family: Internal Services

Req ID: 413109

Employer: Siemens Industry Software Inc.

Job Title: Senior Product Engineering Manager [MULTIPLE POSITIONS]

Job Location: Fremont, CA

Job Type: Full Time

Rate of Pay: The salary range for this position in Fremont, CA is $174,300.00-$278,900.00 per year and this role is eligible to earn incentive compensation. Siemens offers a variety of health and wellness benefits to employees. Details regarding our benefits can be found here: www.benefitsquickstart.com. In addition, this position is eligible for time off in accordance with Company policies, including paid sick leave, paid parental leave, PTO (for non-exempt employees) or non-accrued flexible vacation (for exempt employees).

Duties: Work on defining Place and Route flow and methodology for designs from networking, mobile, CPU and customer centric domain. Oversee Flow and Methodology of various functions of Aprisa Product line such as Placement, Clock Tree Synthesis, Optimization and Routing. Work on physical design activities for advanced technology nodes. Assess power domain based designs and create methodologies for supporting them in Aprisa, as well as other EDA products. Work with Research and Development Team to further advance the technology offerings. Solve customer's problems for critical designs to achieve desired performance, area, and power targets. Give talks at tradeshows as well as provide product and marketing updates to Aprisa customers.

Assess power domain-based designs and create methodologies for supporting them in Aprisa, as well as other EDA products. Work in the Electronic Design Automation (EDA) industry, specifically in the area of Very Large Scale Integration [VLSI] / Physical design implementation. Work with Digital Implementation Software, such as Aprisa (Aprisa is a detail-route-centric physical design platform for the modern SoC and offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime.). Define methodology through defining flows and steps to be followed for designing chips for Siemens EDA's customers working in the area of CPU, Networking, and 5G applications. Map the requirements into software understandable format from Siemens EDA customers on low-power chip design(Unified Power Format (UPF) and work on its support within Siemens EDA's implementation software. Create project status presentations for delivery to customers or project personnel and work with Siemens EDA's customers to address their requirements for achieving power, area and throughput targets using Siemens EDA digital implementation software. Interpret requirements on advanced process nodes like 5nm, 3nm from various foundries and work on getting them implemented in Siemens EDA digital implementation software. Architect innovative techniques to advance Siemens EDA's digital implementation software in the market place. Confer with project personnel to identify and resolve problems. Monitor project milestones and deliverables and schedule or facilitate project meetings. Produce and distribute project documents. Submit project deliverables to clients, ensuring adherence to quality standards.

Requirements : Employer will accept a Bachelor's degree, or foreign equivalent, in Electrical Engineering, Electronics Engineering or related field and 60 months of experience in the job offered or in a Product Management related occupation.

  1. Working with advanced FinFet nodes from leading foundries

  2. Working with physical design flows from placement, clock tree synthesis and routing;

  3. Debugging performance, power, and area designs by utilizing advanced P&R tool features;

  4. Working with UPF (Unified power format) for EDA products;

  5. TCL and PERL scripting;

  6. Working with Physical Design (floorplan, placement, CTS and routing), mainstream P&R tools for timing closure of blocks or Full Chip designs;

  7. Working with commercial place and route tools such as Synopsys-ICC2/FC, Cadence-Innovus, or Siemens-Aprisa;

  8. Physical design implementation of two or more projects.

Referral Program: Incentives offered through the Company’s Employee Referral Program are applicable to this position.

CONTACT : Apply within this posting

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