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Cypress Semiconductor Corporation seeks a Senior Staff Design Verification Engineer (Lynnwood, WA) to actively participate in definition of Verification infrastructure including test bench components, test cases which are scalable and portable across various projects and platforms. Define verification strategy (constraint random, formal, directed, etc.) for digital or mixed-signal IP/Subsystem and SOC verification. Responsible to work in different verification methodologies including but not limited to UVM, OVM, SV based test benches. Identify, document and execute test plans on verification platforms, develop and debug random constrain verification test suite to fully verify the design under test. Actively participate in cross functional collaboration with design teams to ensure a successful product delivery; work with post-Silicon teams to bring up and assist in validation testing. Responsible to initiate constant improvements in the verification methodologies.

Salary Range: $147,576 to $179,078.77 per year

JOB REQUIREMENTS:

Requires a Bachelor's degree in Electrical Engineering or a related field and 7 years of experience in IC digital design or design verification related function. Alternatively, the company would accept a Master's degree in Electrical Engineering and 5 years of experience in IC digital design or design verification related function. Must have the following experience: Verification methodologies including UVM, OVM, and System Verilog; Developing verification infrastructure for complex digital or mixed-signal IPs/Sub-systems or SoCs including development of test cases, scoreboard, SystemVerilog Assertions; Digital and/or mixed-signal design; Protocols including AHB, AMBA, AXI, SPI, LIN, and UART; Functional coverage, code coverage, other coverage metrics; Power aware verification using UPF and Gate level simulation; and C, python, tcl, and Perl for developing test content and scripts.

Email resumes to: JobApplication@infineon.com ref. job code ST114 when applying.